Will tools ever exist that can close the design gap? Bryan Ackland, chairman of the 39th Design Automation Conference, being held in New Orleans this month, has his doubts.
In our cover story, Ackland, vice president of communications systems technology at Agere Systems, examines the challenges affecting the design of next-generation communication systems-on-chip, including timing closure of large digital blocks, signal integrity in both the analog and digital sections, power distribution and the database limitations imposed by 32-bit tools. Specifically, he looks at the challenges that Agere faced in designing a transceiver add/drop multiplexer chip, given the abilities and limitations of the tools available to its design teams at the time.
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Ackland acknowledges that continuing advances in process technology enable designers, in principle, to develop ever more complex communications SoC devices at higher speeds. But those very complexities, he argues, create a crisis in which designers spend ever more time iterating through cycles of synthesis, place and route, and physical verification. Some modules of the TADM design required 12 to 14 such iterations to achieve closure.
To generate a design that is truly correct by construction, Ackland writes, a design flow is needed that can predict physical-layout parameters based on accurate models early in the process.
Then comes the zinger: If that proves intractable, Ackland asserts, designers may need to develop a radical approach that sacrifices some measure of density and performance to achieve reasonable design times, as they once did in the transition from full-custom to standard cells.
We're not so sure the industry can go back to the standard-cell days: Sophisticated systems-on-chip for comms typically require high-speed, high-bandwidth mixed-signal interfaces; large, complex digital blocks that implement multilayer protocols; and copious amounts of on-chip memory. But it is certainly true that designers of those devices push the limits of EDA tools. Ackland comes down hard on the tool community, calling for solutions that are "correct by construction," not "correct by iteration."
For the increasing signal-integrity problems, Ackland says, tools are needed that generate correct solutions based on shielding, spacing and added drivers, far earlier in the design process. Tools should also run on 64-bit machines. And transferring design data among dispersed teams is forcing a "sneaker net" methodology: With his teams located about 100 miles apart, Ackland writes, it proved quicker to drive a tape from one location to another than to send a large design file electronically.
Indeed, there are plenty of challenges that need to be addressed in order to meet the goals of system-on-chip designs with the tools available to designers. And there are plenty of alternative methodologies that deserve an airing.
While ISD has been a forum for just such discussions, we are sad to report that this is the magazine's final issue. When we took over this "Journal of the Design Process" last June, as the 38th Design Automation Conference was unfolding, the design gap was already an entrenched problem. The gap has only widened over the past year.
So while ISD in its current form will be no more, rest assured that we will continue to cover the intricacies and issues of integrated systems design in the pages of EE Times and online at EEdesign, bringing you the depth of coverage and the sophisticated perspective you require and deserve.
Thanks for the memories.
http://www.isdmag.com
Copyright © 2002 CMP Media LLC
6/1/02, Issue # 14156, page 4.
